This document relates to integrated circuits, and more particularly to assemblies having dies that include semiconductor integrated circuits.
In fabrication of integrated circuits, one or more circuits are manufactured in a semiconductor wafer and are then separated into “dies” (also called “chips”) in a process called “singulation” or “dicing”. The dies, such as shown at 110 in FIG. 1, are attached to a wiring substrate (“WS”, e.g. printed wiring board) 120 which has conductive lines 130 connecting the dies to each other and to other elements of the system. More particularly, the dies have contact pads 110C connected to the dies' circuits (not shown), and these contact pads are attached to contact pads 120C of WS 120. Pads 120C are interconnected by conductive lines 130. The attachment of pads 110C to pads 120C is performed by connections 140 which may include solder, conductive epoxy, or other types.
Encapsulant 150 (e.g. epoxy with silica or other particles) protects the dies 110 and the connections 140 from moisture and other contaminants, ultraviolet light, alpha particles, and possibly other harmful elements. The encapsulant also strengthens the die-to-WS attachment against mechanical stresses, and the encapsulant helps conduct heat away from the dies (to an optional heat sink 160 or directly to the ambient (e.g. air)). However, the encapsulant can cause warpage if the encapsulant's thermal expansion coefficient (CTE) does not match the CTE of the dies or the WS.
The wiring substrate can be an interposer, i.e. an intermediate substrate used to accommodate a mismatch between die fabrication technology and printed wiring substrates (PWS). More particularly, the die's contact pads 110C can be placed much closer to each other (at a smaller pitch) than PWS pads 120C. Therefore (FIG. 2), an intermediate substrate 120.1 can be used between the dies 120 and the PWS (shown at 120.2). Interposer 120.1 includes a substrate 120.1S (e.g. semiconductor or other material), a redistribution layer (RDL) 210.T on top of substrate 120.1S, and another redistribution layer 210.B on the bottom of substrate 120.1S. Each RDL 210.T, 210.B includes interconnect lines 216 insulated from each other and from substrate 120.1S by the RDL's dielectric 220. Lines 216 are connected to contact pads 120.1C.T on top of the interposer and contact pads 120.1C.B on the bottom. Lines 216 of RDL 210.T are connected to lines 216 of RDL 210.B by conductive (e.g. metallized) through-vias 224. Pads 120.1C.T are attached to the dies' pads 110C by connections 140.1 as in FIG. 1. Pads 120.1C.B are attached to pads 120.2C of PWS 120.2 by connections 140.2. Pads 120.1C.B are at a larger pitch than pads 120.1C.T, to accommodate the pitch of the PWS contacts 120.2C.
The interposer substrate 120.1S should be as thin as possible to shorten the signal paths between dies 110 and PWS 120.2 and thus make the system faster and less power hungry. Also, if the interposer is thin, fabrication of metallized vias 224 is facilitated. However, thin interposers are hard to handle: they are brittle, easily warped, and do not absorb or dissipate heat during fabrication. Therefore, a typical fabrication process attaches the interposer to a temporary substrate (“support wafer”) during fabrication. The support wafer is later removed. Attaching and detaching temporary support wafers is burdensome, and should be avoided if possible. See U.S. Pat. No. 6,958,285 issued Oct. 25, 2005 to Siniaguine.
It is desirable to provide improved protection of dies from mechanical stresses, heat, and harmful elements, and improved accommodations for thin interposers.